1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a column select signal generation circuit.
2. Related Art
In general, a semiconductor memory apparatus selects a word line and a bit line according to an outside address input, and accesses a memory cell connected between the selected word line and bit line to perform a read or write operation.
FIG. 1 is a configuration diagram of a conventional semiconductor memory apparatus.
Referring to FIG. 1, the conventional semiconductor memory apparatus 10 includes a control logic 100, a memory cell array 101, a row address buffer 103, a row decoder 105, a word line driver 107, a column address buffer 109, a column decoder 111, and a sense amplifier/write driver block (SA/WD) 113.
In order to access a specific memory cell, the row decoder 105 decodes a row address based on an outside input and generates a word line driving signal, and the column decoder 111 decodes a column address ADD_C and generates a column select signal YI.
FIG. 2 is a configuration diagram of the conventional column decoder.
The column decoder 20 includes a decoding unit 22 and a column select signal generation unit 24. The decoding unit 22 is configured to output pre-decoded signals LAY345<0:7>, LAY67<0:3>, and LAY89<0:3> in response to a strobe signal STRB and a column address latch signal AYT<3:9> obtained by latching the column address ADD_C. The column select signal generation unit 24 is configured to combine the output signals of the decoding unit 22 to output the column select signal YI.
The decoding unit 22 may include a first decoder 201, a fourth decoder 207, a second decoder 203, and a third decoder 205. The first decoder 201 is configured to decode a first column address latch signal AYT<3:5>. The fourth decoder 207 is configured to generate the first pre-decoded signal LAY345<0:7> in response to an output signal of the first decoder 201 and the strobe signal STRB. The second decoder 203 is configured to generate the second pre-decoded signal LAY67<0:3> by decoding a second column address latch signal AYT<6:7>. Similarly, the third decoder 205 is configured to generate the third pre-decoded signal LAY89<0:3> by decoding a third column address latch signal AYT<8:9>.
The column select signal generation unit 24 includes a first driver 209, a current controller 211, and a second driver 213. The first driver 209 is driven in response to the first pre-decoded signal LAY345<0:7> and connected to a power supply voltage terminal VDD. The current controller 211 is connected to the first driver 209, and configured to control the voltage of the first driver 209 according to a combination of the second and third pre-decoded signals LAY67<0:3> and LAY89<0:3>. The second driver 213 is connected to an output terminal of the first driver 209 and configured to output the column select signal YI.
FIG. 2 illustrates an example in which the column decoder 20 generates 128 (8*4*4) column select signals YI using the column address latch signal AYT<3:9>.
Since the column select signal YI outputted from the second driver 213 must drive a very long metal line, transistors P2 and N2 forming the second driver 213 are designed to have a large size.
However, when the column select signal YI is outputted as a low level, the switching element P2 of the second driver 213 is turned off, and the switching element N2 is turned on. Therefore, a leakage current inevitably flows into a ground terminal through the switching element N2. Furthermore, since several thousands of second drivers 213 may exist depending on the capacity of the memory apparatus, the leakage current in an off state occupies a considerable portion of the entire operation current of the memory apparatus.